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3C19 MC141511A motorola lcd segment driver cmos the MC141511A is an lcd frontplane (segment) driver chip which in- cludes a 656 x 8 display ram. the mc68hc05l10 microcomputer is the companion device which provides the backplane drive. the mc68hc05l10, together with one MC141511A, may be used to drive a 5248-pixel muxed-by-41 display or a 4096-pixel muxed-by-32 dis- play. larger displays may be driven by adding additional MC141511A. the MC141511A is a low operating voltage version of mc141511. it is pin to pin compatible to the mc141511. see application note an-hk-13a. ? operating supply voltage range - control logic, ram, and latch (vdd pin): 2.7v to 5.5v frontplane drivers (vlcd pin): 4.5v to 13.2v ? operating temperature range: -20 to 70?c ? direct interface with the mc68hc05l10 ? 656 x 8 static ram (display ram) ? 128 lcd segment (frontplane) driving signals ? 10-bit address bus and 8-bit bidirectional data bus ? selectable 1:32 or 1:41 multiplex ratios ? available in two forms: tab (tape automated bonding), 161 contacts, 10 sprocket hole device die form without gold bumps, 159 pads with 4.5 mil pads pitch con trol logi c dis play ram l cd data latch segment driver a0-a9 d0-d7 v lcd v segh v segl v ss r/w bpclk ce lrs phi2 bps ync driver outputs ms vdd lev el selector block diagram MC141511A MC141511At2 tab mcc141511a die ordering information mcc141511a bare die MC141511At2 tab motorola semiconductor technical data rev 3 10/96
motorola 3C20 MC141511A figure 1a. tab package contact assignment (copper view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
3C21 MC141511A motorola figure 1b. chip pad assignment
motorola 3C22 MC141511A symbol parameter value unit v dd supply voltage -0.3 to +7.0 v v lcd -0.3 to +14.0 v v in input voltage v ss -0.3 to v dd +0.3 v i current drain per pin excluding v dd and v ss 25 ma t a operating temperature -20 to +70 ?c t stg storage temperature range -65 to +150 ?c maximum ratings* (voltages referenced to v ss , t a = 25?c) * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin description section. symbol parameter min typ max unit v dd v lcd operating voltage supply voltage lcd voltage 2.7 4.5 - - 5.5 13.2 v v i ac i dp i sb i ac i dp i sb supply current at v dd =5.5v (phi2=3.685mhz) access display standby (using d on bit of the mcu) at v dd =3.0v (phi2=1.25mhz) access display standby (using d on bit of the mcu) - - - - - - - 25 15 - 17 10 200 30 20 200 30 20 ua ua ua ua ua ua i lcd supply current at v lcd - - 200 ua v ol v oh output voltage, iload210.0ua - v lcd -0.1 - - 0.1 - v v v oh output high voltage (iload=1.6ma) d7-d0 v dd -0.8 - - v v ol output low voltage (iload=1.6ma) d7-d0 - - 0.4 v v ih input high voltage r/ w, bpclk, bpsync, phi2, ms, ce, d7-d0 0.8xv dd -v dd v v il input low voltage r/ w, bpclk, bpsync, phi2, ms, ce, d7-d0 v ss - 0.2xv dd v v r data retention 2.0 - - v i in input current bpclk, bpsync, r/ w, phi2, d7-d0 - - 1 ua c in capacitance r/ w, bpclk, bpsync, phi2, ms, ce, d7-d0 - - 8 pf i oh i ol output current (v oh =4.5v, v ol =0.5v) d7-d0 +20 - - - - -20 ua ua electrical characteristics (voltage referenced to v ss , t a = 25?c) this device contains circuitry to protect the inputs against damage due to high static voltages or elec- tric ?elds; however, it is advised that normal precau- tions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recom- mended that v in and v out be constrained to the range v ss < or = (v in or v out ) < or = v dd . reliability of operation is enhanced if unused input are con- nected to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. this device may be light sensitive. caution should be taken to avoid exposure of this device to any light source during normal operation. this device is not radiation protected.
3C23 MC141511A motorola ac electrical characteristics - write cycle (v dd =3.0v 10 %, v ss =0v) symbol parameter min max unit t cycw write cycle time 400 - ns t as address set up time 100 - ns t ah address hold time 70 - ns t cs chip select pulse width 260 - ns t wcs write to chip select delay time 100 - ns t dsw data setup time 200 - ns t h input hold time 15 - ns t wh write hold time from chip select 70 - ns figure 2. write cycle timing ce phi2 r/w d0-7 t cycw t as t cs t ah t wh t wcs t dsw t h data in stable
motorola 3C24 MC141511A ac electrical characteristics - read cycle (v dd =3.0v 10 %, v ss =0v) symbol parameter min max unit t cycr read cycle time 400 - ns t as address setup time 100 - ns t ddr data delay time (read) - 350 ns t h output hold time 10 - ns figure 3. read cycle timing ce phi2 t cycr t ddr d0-7 data valid t as t h
3C25 MC141511A motorola v dd and v ss the main dc power is supplied to the part by these two connec- tions. v dd is the most-positive supply level for logic circuitry and v ss is ground. v lcd this supply connection provides the voltage level for the segment drivers and is connected to the vout connection of the mc68hc05l10 mcu. v segl , v segh these inputs are connected to v2 and v3 of an external voltage divider. see figure 4. d0 - d7 these connections form an eight bit wide bidirectional data bus which are connected to d0 through d7 of the mc68hc05l10. a0 - a9 these inputs form a ten-bit wide address bus for addressing the display ram and are connected to a0 through a9 of the mc68hc05l10. bpsync this input is a periodic active-low signal from the mc68hc05l10 for timing synchronization. bpsync is connected to frm of mc68hc05l10. see figure 5. bpclk this input may be run as high as 4.096 khz (50% duty cycle). it provides the required frame frequency for the segment driver. it is con- nected to bpclk of the mc68hc05l10. thus, the frequency is usually 2.048 khz. see figure 5. phi2 this input is a bus clock input that is used for data bus timing syn- chronization. it is connected to p02 of mc68hc05l10. seg0 - seg127 these 128 output lines provide the frontplane drive signals to the lcd panel. these outputs are forced to a low level while display is turned off. any unused segment outputs should be left open. ce this is an active low chip enable input and is connected to either cs1, cs2, cs3 or cs4 of the mc68hc05l10. lrs the left-right selection input de?nes the direction of the segment driver display. see figure 8. 0 or low = seg 0 - 127 1 or high = seg 127 - 0 ms this input selects how display ram is addressed. either a 1:32 or 1:41 multiplex ratio is possible. 0 or low = 1:32 multiplex addressing 1 or high = 1:41 multiplex addressing r/ w this input indicates which direction the data is to be passed over the data bus. when r/ w is low, the lcd driver reads data from the data bus (d0-d7). when r/ w is high, the lcd driver writes data to the data bus (d0-d7). this input is connected to r/w of mc68hc05l10. test allowing this connection to ?oat or connecting it to vss (gnd) places the part in the normal mode of operation. this input has an on- chip pulldown resistance of approximately 1m?. pin descriptions figure 4. external voltage divider v3 v2
motorola 3C26 MC141511A figure 5. relationship between bpsync and bpclk figure 6. display ram con?guration lrs = 1 lrs = 0 80 00 01 02 03 81 7e ff 101 103 102 100 17f 180 1ff 181 182 183 1fe 17e fe 7f a byte b0 b7 82 83 201 203 202 200 27f 27e 280 28f 204 205 206 207 b0 b7 seg0 seg1 seg2 seg3 seg127 seg126 seg125 seg124 seg126 seg127 seg1 seg0
3C27 MC141511A motorola operation of lcd driver introduction the mc141511 is lcd driver with selectable 1: 32 or 1: 41 multi- plex ratios. the device consists of the following functional blocks as shown in the block diagram. control logic - accepts the control signals from the mcu and generates internal signals for synchronisation. display ram - stores the display data. each bit of the display ram has one-to-one correspondence to a pixel of the lcd. the display ram is in vertical byte oriented format as shown in figure 6 and the way the display ram is addressed depends on the multiplexing mode of the lcd (figure 8). with reference to figure 6, the display ram also contains 16 bytes of memory which is in horizontal format ($280-$28f). the display ram is addressed when backplane reaches 41. level selector - consists of a switching circuit to select appropriate voltage levels from an external voltage divider. see ?gure 4. segment drivers - provides the segment driving signals to the lcd frontplane. see figure 7. the lcd driver clock is derived from the 2.048khz bpclk and frame frequency is 64 hz for 1:32 multiplex and 50 hz for 1:41 multiplex ratio. see figure 5. generation of lcd bias levels refer to figure 4. in order to obtain optimum contrast for lcd panels, the bias levels should be selected such that bias = r/(4r+r1) = 1/(? mux + 1) v1/vlcd = 1/(? mux + 1) v2/vlcd = 2/(? mux + 1) v3/vlcd = (? mux - 1)/(? mux + 1) v4/vlcd = ? mux /(? mux + 1) example: mux = 41 ----- bias = 1: 7.4, r = 10k, r1 = 33k, vr = 100k mux = 32 ----- bias = 1: 6.6, r = 10k, r1 = 27k, vr = 100k
motorola 3C28 MC141511A 1 2 3 4 n 1 2 3 4 n 1 2 com (1) com (2) seg (x) seg (x)- com (1) seg (x)- com (2) 1 frame gnd v1 v2 v3 v4 v lcd v1 v2 v3 v4 v1 v2 v3 v4 v1 v2 v3 v4 -v4 -v3 -v2 -v1 v1 v2 v3 v4 -v4 -v3 -v2 -v1 n = 32, 41 bpsync (signal from mcu, frm pin) gnd v lcd gnd v lcd gnd v lcd -v lcd gnd v lcd -v lcd figure. 7 driving waveform of 1:5 bias, 1:32 or 1:41 multiplex ratio 2 frames = 1/32 or 1/25 sec
3C29 MC141511A motorola one slave $200 - $27f $280 - $2ff $300 - $37f $380 - $3ff 1 : 32 $400 - $47f $480 - $4ff $500 - $57f $580 - $5ff $480 - $4ff $500 - $57f $580 - $5ff $600 - $67f 1 : 41 $680 - $6ff two slaves three slaves $200 - $27f $280 - $2ff $300 - $37f $380 - $3ff $400 - $47f $200 - $27f $280 - $2ff $300 - $37f $380 - $3ff 1 : 32 $200 - $27f $280 - $2ff $300 - $37f $380 - $3ff 1 : 41 $400 - $47f $1c0 - $1cf $1c0 - $1cf $1d0 - $1df 1 : 41 $700 - $77f $780 - $7ff $800 - $87f $880 - $8ff $900 - $97f 1 : 32 $600 - $67f $680 - $6ff $700 - $77f $780 - $7ff $200 - $27f $280 - $2ff $300 - $37f $380 - $3ff $400 - $47f $480 - $4ff $500 - $57f $580 - $5ff $480 - $4ff $500 - $57f $580 - $5ff $600 - $67f $680 - $6ff $200 - $27f $280 - $2ff $300 - $37f $380 - $3ff $400 - $47f $1c0 - $1cf $1d0 - $1df $1e0 - $1ef 1 : 32 $800 - $87f $880 - $8ff $900 - $97f $980 - $9ff $600 - $67f $680 - $6ff $700 - $77f $780 - $7ff $200 - $27f $280 - $2ff $300 - $37f $380 - $3ff $400 - $47f $480 - $4ff $500 - $57f $580 - $5ff 1 : 41 four slaves $980 - $9ff $a00 - $a7f $a80 - $aff $b00 - $b7f $b80 - $bff $700 - $77f $780 - $7ff $800 - $87f $880 - $8ff $900 - $97f $480 - $4ff $500 - $57f $580 - $5ff $600 - $67f $680 - $6ff $200 - $27f $280 - $2ff $300 - $37f $380 - $3ff $400 - $47f $1d0 - $1df $1e0 - $1ef $1f0 - $1ff $1c0 - $1cf figure 8. display ram mapping for 1:32 and 1:41 multiplex ratio
motorola 3C30 MC141511A package dimensions MC141511At2 tab package dimension (do not scale this drawing) reference: 98asl00183a issue a released on 04/15/96 copper polyimide
3C31 MC141511A motorola MC141511At2 tab package dimension (do not scale this drawing) reference: 98asl00183a issue a released on 04/15/96
motorola 3C32 MC141511A notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter 3. copper thickness: 1 oz MC141511At2 tab package dimension millimeters inches millimeters inches dim min max min max dim min max min max a 46.55 47.55 1.8327 1.8720 ae 21.25 21.35 0.8366 0.8406 b 34.775 35.175 1.3691 1.3848 af 1.95 2.05 0.0768 0.0807 c 28.947 29.007 1.1396 1.1420 ag 0.85 0.95 0.0335 0.0374 d 4.72 4.78 0.1858 0.1882 ah 0.85 0.95 0.0335 0.0374 e 1.951 2.011 0.0768 0.0792 aj 9.75 9.85 0.3839 0.3878 f 1.951 2.011 0.0768 0.0792 ak 6.85 6.95 0.2697 0.2736 g 1 2 0.0394 0.0787 al 4.75 4.85 0.1870 0.1909 h - - - - am 1.95 2.05 0.0768 0.0807 j 7.469 8.469 0.2941 0.3334 an 1.95 2.05 0.0768 0.0807 k 9.04 10.04 0.3559 0.3953 ap 0.085 0.095 0.0033 0.0037 l 0.48 0.52 0.0189 0.0205 ar 0.35 0.45 0.0014 0.0177 m 1.26 1.28 0.0496 0.0504 as 0.35 0.45 0.0014 0.0177 n 4.95 5.05 0.1949 0.1988 at 0.6 0.7 0.0236 0.0276 p 20.45 20.55 0.8051 0.8091 au 0.6 0.7 0.0236 0.0276 r 20.45 20.55 0.8051 0.8091 av 0.75 0.85 0.0295 0.0335 s 9.78 9.88 0.3850 0.3890 aw 0.75 0.85 0.0295 0.0335 t 23.155 23.255 0.9116 0.9156 ax 1.75 1.85 0.0689 0.0728 u 23.155 23.255 0.9116 0.9156 ay 0.34 0.36 0.0134 0.0142 v 22.53 22.62 0.8870 0.8905 az 0.15 0.19 0.0059 0.0075 w 22.53 22.62 0.8870 0.8905 ba 13.7 14.3 0.5394 0.5630 x 23.1 23.2 0.9094 0.9134 bb 1.22 1.32 0.0480 0.0520 y 23.1 23.2 0.9094 0.9134 bc 1.22 1.32 0.0480 0.0520 z 19.95 20.05 0.7854 0.7894 bd 0.45 0.55 0.0177 0.0217 aa - 0.2 - 0.0079 be 11.35 11.45 0.4469 0.4508 ab 0.686 0.838 0.027 0.033 bf 0.12 0.22 0.0047 0.0087 ac 0.068 0.063 0.0027 0.0024 bg 12.35 12.45 0.4862 0.4902 ad 0.579 0.629 0.0227 0.0247 reference: 98asl00183a issue a released on 04/15/96
3C33 MC141511A motorola MC141511At2 reference: 98asl00183a issue a released on 04/15/96
motorola 3C34 MC141511A mcc141511a pad coordinates (unit: um) pin pin pin pin name x y name x y name x y name x y vdd -1874.62 -2498.76 seg126 2728.66 -2233.88 seg86 2630.76 2432.32 seg39 -2728.66 2227.72 test -1738.66 -2498.76 seg125 2728.66 -2119.48 seg85 2516.36 2432.32 seg38 -2728.66 2113.32 bpsync -1611.06 -2498.76 seg124 2728.66 -2005.08 seg84 2401.96 2432.32 seg37 -2728.66 1998.92 bpclk -1483.46 -2498.76 seg123 2728.66 -1890.68 seg83 2287.56 2432.32 seg36 -2728.66 1884.52 ms -1355.86 -2498.76 seg122 2728.66 -1776.28 seg82 2173.16 2432.32 seg35 -2728.66 1770.12 phi2 -1228.26 -2498.76 seg121 2728.66 -1661.88 seg81 2058.76 2432.32 seg34 -2728.66 1655.72 ce -1100.66 -2498.76 seg120 2728.66 -1547.48 seg80 1944.36 2432.32 seg33 -2728.66 1541.32 r w -973.06 -2498.76 seg119 2728.66 -1433.08 seg79 1829.96 2432.32 seg32 -2728.66 1426.92 a9 -845.46 -2498.76 seg118 2728.66 -1318.68 seg78 1715.56 2432.32 seg31 -2728.66 1312.52 a8 -717.86 -2498.76 seg117 2728.66 -1204.28 seg77 1601.16 2432.32 seg30 -2728.66 1198.12 a7 -590.26 -2498.76 seg116 2728.66 -1089.88 seg76 1486.76 2432.32 seg29 -2728.66 1083.72 a6 -462.66 -2498.76 seg115 2728.66 -975.48 seg75 1372.36 2432.32 seg28 -2728.66 969.32 a5 -335.06 -2498.76 seg114 2728.66 -861.08 seg74 1257.96 2432.32 seg27 -2728.66 854.92 a4 -207.46 -2498.76 seg113 2728.66 -746.68 seg73 1143.56 2432.32 seg26 -2728.66 740.52 a3 -79.86 -2498.76 seg112 2728.66 -632.28 seg72 1029.16 2432.32 seg25 -2728.66 626.12 a2 47.74 -2498.76 seg111 2728.66 -517.88 seg71 914.76 2432.32 seg24 -2728.66 511.72 a1 175.34 -2498.76 seg110 2728.66 -403.48 seg70 800.36 2432.32 seg23 -2728.66 397.32 a0 302.94 -2498.76 seg109 2728.66 -289.08 seg69 685.96 2432.32 seg22 -2728.66 282.92 lrs 430.54 -2498.76 seg108 2728.66 -174.68 seg68 571.56 2432.32 seg21 -2728.66 168.52 d0 558.14 -2498.76 seg107 2728.66 -60.28 seg67 457.16 2432.32 seg20 -2728.66 54.12 d1 685.74 -2498.76 seg106 2728.66 54.12 seg66 342.76 2432.32 seg19 -2728.66 -60.28 d2 813.34 -2498.76 seg105 2728.66 168.52 seg65 228.36 2432.32 seg18 -2728.66 -174.68 d3 940.94 -2498.76 seg104 2728.66 282.92 seg64 113.96 2432.32 seg17 -2728.66 -289.08 d4 1068.54 -2498.76 seg103 2728.66 397.32 seg63 -0.44 2432.32 seg16 -2728.66 -403.48 d5 1196.14 -2498.76 seg102 2728.66 511.72 seg62 -114.84 2432.32 seg15 -2728.66 -517.88 d6 1323.74 -2498.76 seg101 2728.66 626.12 seg61 -229.24 2432.32 seg14 -2728.66 -632.28 d7 1451.12 -2498.76 seg100 2728.66 740.52 seg60 -343.64 2432.32 seg13 -2728.66 -746.68 vlcd 1578.94 -2498.76 seg99 2728.66 854.92 seg59 -458.04 2432.32 seg12 -2728.66 -861.08 vsegh 1706.54 -2498.76 seg98 2728.66 969.32 seg58 -572.44 2432.32 seg11 -2728.66 -975.48 vsegl 1834.14 -2498.76 seg97 2728.66 1083.72 seg57 -686.84 2432.32 seg10 -2728.66 -1089.88 vss 1979.78 -2498.76 seg96 2728.66 1198.12 seg56 -801.24 2432.32 seg9 -2728.66 -1204.28 dumpad 4 2111.78 -2498.76 seg95 2728.66 1312.52 seg55 -915.64 2432.32 seg8 -2728.66 -1318.68 dumpad 3 2239.38 -2498.76 seg94 2728.66 1426.92 seg54 -1030.04 2432.32 seg7 -2728.66 -1433.08 dumpad 2 2366.98 -2498.76 seg93 2728.66 1541.32 seg53 -1144.44 2432.32 seg6 -2728.66 -1547.48 dumpad 1 2494.58 -2498.76 seg92 2728.66 1655.72 seg52 -1258.84 2432.32 seg5 -2728.66 -1661.88 seg127 2619.54 -2498.76 seg91 2728.66 1770.12 seg51 -1373.24 2432.32 seg4 -2728.66 -1776.28 seg90 2728.66 1884.52 seg50 -1487.64 2432.32 seg3 -2728.66 -1890.68 seg89 2728.66 1998.92 seg49 -1602.04 2432.32 seg2 -2728.66 -2005.08 seg88 2728.66 2113.32 seg48 -1716.44 2432.32 seg1 -2728.66 -2119.48 seg87 2728.66 2227.72 seg47 -1830.84 2432.32 seg0 -2728.66 -2233.88 seg46 -1945.24 2432.32 seg45 -2059.64 2432.32 seg44 -2174.04 2432.32 seg43 -2288.44 2432.32 seg42 -2402.84 2432.32 seg41 -2517.24 2432.32 seg40 -2631.64 2432.32 die size : 240.0 x 212.0 mil 2 pad pitch : 4.5 mil note : 1 mil ~ 25.4 m dumpad 1-4: dummy pad without connections to internal circuitry
3C35 MC141511A motorola 10k 10k 30k 10k 10k typical applications 128 x 41 single panel lcd system with mc68hc05l10 41 x 128 dots lcd panel seg0-seg127 bp0-bp40 mc68hc05l10 bp0-bp40 MC141511A seg0-seg127 bpclk frm cs1 r/ w po2 a0-a9 d0-d7 vlcd vsegh vsegl bpclk bpsync ce ms lrs r/ w phi2 vdd vss vlcd vout v4 v1 trimmer for contrast control lcd power supply v4 v3 v2 v1 a0-a9 d0-d7 vdd vss 10 8 note : full capability of mc68hc05l10 can control up to four MC141511A slave lcd drivers with 41 x 512 dots lcd panel. refer to application note, mc68hc05l10 an enhanced version of l9 for handheld equipment appli- cations (an-hk-13a) for more details. +5v +5v +5v

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